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DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
M3D109
BSS192 P-channel enhancement mode vertical D-MOS transistor
Product specification Supersedes data of 1997 Jun 20 2002 May 22
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
FEATURES * Direct interface to C-MOS, TTL, etc. * High-speed switching * No secondary breakdown. APPLICATIONS * Line current interrupter in telephone sets * Relay, high-speed and line transformer drivers. DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a SOT89 package.
1 Bottom view 2 3
MAM354
BSS192
PINNING - SOT89 PIN 1 2 3 SYMBOL s d g drain gate DESCRIPTION source
handbook, halfpage
d
g
s
Marking code: KB.
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA SYMBOL VDS VGSth ID RDSon PARAMETER drain-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance ID = -200 mA; VGS = -10 V ID = -1 mA; VGS = VDS CONDITIONS MAX. -240 -2.8 -200 12 V V mA UNIT
2002 May 22
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS VGSO ID IDM Ptot Tstg Tj Note 1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm. THERMAL CHARACTERISTICS SYMBOL Rth j-a Note 1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm. CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS VGSth IDSS IGSS RDSon yfs Ciss Coss Crss ton toff PARAMETER drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current drain-source on-state resistance forward transfer admittance input capacitance output capacitance reverse transfer capacitance CONDITIONS VGS = 0; ID = -10 A VGS = VDS; ID = -1 mA VGS = 0; VDS = -60 V VGS = -0.2 V; VDS = -200 V VDS = 0; VGS = 20 V VGS = -10 V; ID = -200 mA VDS = -25 V; ID = -200 mA VGS = 0; VDS = -25 V; f = 1 MHz VGS = 0; VDS = -25 V; f = 1 MHz VGS = 0; VDS = -25 V; f = 1 MHz VGS = 0 to -10 V; VDD = -50 V; ID = -250 mA VGS = -10 to 0 V; VDD = -50 V; ID = -250 mA MIN. -240 -0.8 - - - - 60 - - - - - TYP. - - - -0.1 - 10 200 55 20 5 PARAMETER thermal resistance from junction to ambient note 1 CONDITIONS VALUE 125 PARAMETER drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature Tamb 25 C; note 1 open drain CONDITIONS - - - - - -65 - MIN.
BSS192
MAX. -240 20 -200 -600 1 +150 150 V V
UNIT
mA mA W C C
UNIT K/W
MAX. UNIT - -2.8 -200 -60 100 12 - 90 30 15 V V nA A nA mS pF pF pF
Switching times (see Figs 2 and 3) turn-on time turn-off time 5 20 10 30 ns ns
2002 May 22
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSS192
handbook, halfpage
VDD = -50 V
handbook, halfpage
10 %
INPUT 90 %
10 %
0V -10 V ID 50
MBB689
OUTPUT 90 % ton toff
MBB690
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
handbook, halfpage
1.2
MLC697
handbook, halfpage
160
MDA180
Ptot (W)
C (pF) 120
0.8
80
(1)
0.4 40
(2) (3)
0 0 50 100 150 200 Tamb (C)
0 0
-5
-10
-15
-20 -25 VDS (V)
VGS = 0; Tj = 25 C; f = 1 MHz. (1) Ciss. (2) Coss. (3) Crss.
Fig.5 Fig.4 Power derating curve.
Capacitance as a function of drain-source voltage; typical values.
2002 May 22
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSS192
handbook, halfpage
-1
MDA177
ID (A) -0.8
(1) (2)
handbook, halfpage
-1
MDA178
ID (A) -0.8
-0.6
(3)
-0.6
-0.4
(4)
-0.4
-0.2
(5)
-0.2
0 0
-5
-10
-15
-20 -25 VDS (V)
0 0
-2
-4
-6
-8 -10 VGS (V)
Tj = 25 C. (1) VGS = -10 V. (2) VGS = -6 V.
(3) VGS = -5 V. (4) VGS = -4 V. (5) VGS = -3 V.
VDS = -10 V; Tj = 25 C.
Fig.6 Output characteristics; typical values.
Fig.7 Transfer characteristic; typical values.
-103 handbook, halfpage
MDA179
(1) (2)
handbook, halfpage
1.2 k
MDA182
ID (mA)
1.1
(3)
1 -102 0.9
0.8
-10
8
12
16
20
24 28 RDSon ()
0.7 -50
0
50
100
Tj (oC)
150
Tj = 25 C. (1) VGS = -10 V. (2) VGS = -5 V. (3) VGS = -4 V.
V GSth at T j k = ------------------------------------V GSth at 25C VGSth at ID = -1 mA.
Fig.8
Drain current as a function of drain-source on-state resistance; typical values.
Fig.9
Temperature coefficient of gate-source threshold voltage; typical values.
2002 May 22
5
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSS192
handbook, halfpage
2.5 k 2
MDA181
1.5
1
0.5
0 -50
0
50
100
Tj (oC)
150
R DSon at T j k = ---------------------------------------R DSon at 25 C ID = -200 mA; VGS = -10 V.
Fig.10 Temperature coefficient of drain-source on-state resistance; typical values.
2002 May 22
6
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 3 leads
BSS192
SOT89
D
B
A
b3
E HE
L
1
2
b2
3
c
wM
b1 e1 e
0
2 scale
4 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.6 1.4 b1 0.48 0.35 b2 0.53 0.40 b3 1.8 1.4 c 0.44 0.37 D 4.6 4.4 E 2.6 2.4 e 3.0 e1 1.5 HE 4.25 3.75 L min. 0.8 w 0.13
OUTLINE VERSION SOT89
REFERENCES IEC JEDEC TO-243 EIAJ SC-62
EUROPEAN PROJECTION
ISSUE DATE 97-02-28 99-09-13
2002 May 22
7
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
BSS192
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 May 22
8
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
NOTES
BSS192
2002 May 22
9
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
NOTES
BSS192
2002 May 22
10
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
NOTES
BSS192
2002 May 22
11
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613510/03/pp12
Date of release: 2002
May 22
Document order number:
9397 750 09633

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